1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a Chip Size Package (CSP) whose mounting area is similar to that of a semiconductor chip contained therein.
2. Description of the Prior Art
For semiconductor devices, integration thereof has been increased higher and higher, down-sizing and increasing number of pins have been strongly demanded. For this purpose, surface mount packaging technology in which pins are arranged in a two-dimensional array has been developed. As one of such surface mount packaging technology, BGA (Ball Grid Array) packaging is widely used because of a low cost packaging and good electrical characteristics such as low capacity and inductance. This is a method in which solder balls are arranged in matrix form on the backside of a substrate of a package having mounting area similar to that of a semiconductor chip.
An example of the prior art BGA packaging is described referring to FIG. 1, which shows a printed circuit board 60 having a BGA package thereon.
As shown in FIG. 1, a printed circuit board 60 has a semiconductor device package 50 and a printed interconnection board 40. The semiconductor device package 50 has a semiconductor chip 1 mounted in approximately center on a principal surface of a substrate 58 made of e.g. ceramic. Lead interconnections (not shown) formed on the principal surface of the substrate 58 are connected to external electrode pads arranged on the semiconductor chip 1 through bonding wires 2. The substrate 58 and the semiconductor chip 1 are both sealed for their surfaces so that they are protected from physical and chemical effects in external environments. Solder balls 54, as mounting pads, are arranged in matrix form on the back surface of the substrate 58. The solder balls 54 are connected to the external electrode pads of the semiconductor chip 1 through internal interconnection formed in internal layer of the substrate 58, the lead interconnection on the principal surface of the substrate 58 and bonding wire 2.
A printed interconnection board 40 has a multiple layer structure in which metal interconnections are provided on the principal surface and inner layers thereof. Solder paste 46 is printed on the part where the metal interconnections are to be connected to the solder balls 54 of the semiconductor device package 50.
The printed circuit board 60 is fabricated by placing the printed interconnection board 40 beneath the solder balls 54 of the semiconductor device package 50 and fusing the solder balls 54 using a reflow-process so that the semiconductor device package 50 is connected to the printed interconnection board 40.
The printed circuit board shown in FIG. 1 can thus be fabricated by soldering a semiconductor device package having mounting area similar to that of the chip size, directly to the printed interconnection board, resulting in good electrical characteristics of low capacity and inductance as described above and is widely used as a low cost, small and thin printed circuit board.
In recent years, however, demands for downsizing and decreasing thickness in semiconductor mounting are much more increased. Especially, in the field of computer apparatus, as increasing the need for mobile computers, the demand for reducing the volume, particularly thickness in mounting of semiconductor devices becomes stronger.
As for the conventional printed circuit board 60 shown in FIG. 1, decreasing the occupying area has been sufficiently achieved by employing the CSP structure. By employing FIG. 1, it is explained that the total thickness Tall are the sum of Ta (the thickness of the printed board 5), Tb (the thickness of the solder paste 46), Tc (the thickness of the solder balls 54), Td (the thickness of the substrate 58), Te (the thickness of the semiconductor chip 1), and Tf (the thickness of the resin 3 provided on the top of semiconductor chip 1).
Since the thickness Te of the semiconductor chip 1, and the thickness Ta, Td of substrates 5, 58 respectively are thinned up close to the ultimate limit, it is very difficult to decrease volume for mounting using the conventional structure, consequently it is required to modify the structure of printed circuits.